ASIC​/FPGA Senior Verification Engineer - Milwaukee, WI or Mayfield Heights, OH

ASIC/FPGA Senior Verification Engineer - Milwaukee, WI or Mayfield Heights, OH

Role: ASIC/FPGA Senior Verification Engineer.

Location:

Milwaukee, WI or Mayfield Heights, OH. Duration: 6+ Months.

BGV will be done for the selected candidates.

SCOPE:
Individual Contributor - Responsible for participating in ASIC and FPGA implementation and verification for the Design Services organization.

JOB SUMMARY:

The Engineer will be part of an ASIC/FPGA design team responsible for digital logic design of next generation and legacy products. The candidate will participate in modeling, RTL implementation, conversions and verification. The candidate should be familiar with C, C++ and Verilog and/or VHDL. Must be able to work with supervision from more experienced engineers and engage in technical dialogue.

The candidate should be familiar with ASIC/FPGA verification methodology to be able to create a Verilog/VHDL module test specification from the ASIC/FPGA functional specification and/or module specification created by the chip Architect or ASIC/FPGA Design Engineer. The test specification will include tests needed for the input/outputs, algorithms, state machines, clocks and other design details. The candidate will then implement the tests in VHDL/Verilog/System Verilog languages.

The test code will then be verified in simulation and include coverage analysis of the tests. The candidate should be able to demonstrate the knowledge of ASIC/FPGA test methodology. Knowledge of the System Verilog’s Universal Verification Methodology (UVM) is preferred.

• Basic understanding of CMOS ASIC fundamentals
• Knowledge of all phases of ASIC design and test methodology
• Basic understanding of Timing Analysis
• Verilog / VHDL
• Linux/Unix environment
• Team Player
• Good Communication Skills

• Knowledge of Bus Protocols like AXI, AHB, SPI etc. and Ethernet Protocol
• Knowledge of System Verilog
• Knowledge of UVM
• FPGA based designs
• Test Planning & Verification

A BE / MS or ME / MTech / MS in an Electronics / Electrical Engineering discipline.

Minimum of 5 years’ experience with standard cell ASIC and / FPGA design.

Candidate should be familiar with RTL and gate level design and verification using VHDL and/or Verilog hardware description languages.

Demonstrated ability designing independently for medium/high complexity problems.

Strong oral and written communication skills in English and ability to present technical information.

Please respond with your word resume and requested details:

• Full Name
• Work Authorization
• Contact Number
• Email
• Skype
• Current location
• Willing to relocate
• Rate/hr

All your information will be kept confidential according to EEO guidelines.