FPGA Intern – Custom Compute Hardware

Ludwig Computing FPGA Intern – Custom Compute Hardware Mill Valley, CA
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Internship primarily focused on FPGA-based prototyping and hardware bring-up

Harnessing Randomness, Accelerating Compute;

Creating the Foundational Technology for the Future of Intelligent Compute

About us:

At Ludwig Computing, we are solving the energy efficiency problem of intelligent compute. Our novel co-designed approach is optimized to deliver radical improvements in energy efficiency and performance for various AI workloads. We are building a future where high performance computing is powered by leaner, smarter, and extremely efficient hardware and software platforms. Join us at the ground floor as we build the future of intelligent compute.

About the Role

We are looking for a technically exceptional and intellectually curious Hardware Engineer intern who is passionate about hardware acceleration and wants to work on cutting-edge compute platforms. You will work directly with the founding team to assist in implementing and validating core logics, processing algorithms, and other subsystems. This is a hands-on, research-meets-build role in developing custom blocks for advanced computational workloads.

This internship is primarily focused on FPGA-based prototyping and hardware bring-up
, with opportunities to explore ASIC-relevant design flows and system-level integration in support of broader architectural development. Candidates interested in system-level digital prototyping and early-stage accelerator development are encouraged to apply.

Responsibilities

• Translate architectural concepts into FPGA prototypes
• Design and simulate
  custom processing modules
  using
  Verilog, VHDL, or high-level synthesis (HLS)
• Implement and validate processing components on FPGA platform using industry-standard tools (e.g.,
  Vivado
  ,
  Quartus
  , or
  OpenCL-based flows
  )
• Benchmark performance and optimize tradeoffs in
  latency, area, throughput, and memory bandwidth
• Build test benches, run timing/area analysis, and assist with system integration
• Collaborate with the team to define
  hardware/software boundaries
  , and support bring-up of real demos.

Requirements

• Experience with FPGA development,
  RTL or HLS-based design
  in Verilog/System Verilog, VHDL, or C++
• Familiarity with FPGA development tools (Vivado, Quartus, or equivalent)
• Strong grasp of
  digital logic fundamentals
  , including pipelining and timing closure
• Experience with
  memory mapping and hierarchy
  on FPGA.
• Strong skills in simulation, debugging, and synthesis workflows
• Currently pursuing a degree in engineering (preferably Electrical Engineering, Computer Science)
• Experience with
  OpenCL or HLS-based design targeting FPGA
• Prior
  
  Experience with
  FPGA development boards
• Familiarity with
  hardware/software co-design and system-level integration
• Course work or project experience in digital design, computer architecture, or embedded systems.
• Understanding of
  memory system tradeoffs
• Exposure to
  numerical computing
  , or
  custom arithmetic units
• Exposure to
  ASIC design concepts
  , such as synthesis, floor planning, or RTL-to-GDS tool chains
• Familiarity with
  analog or mixed-signal concepts
• Currently PhD/MS student in EE/CS

What You'll Gain

• Opportunity to work on next generation AI compute architectures
• Hands-on experience building
  novel, high-speed, energy-efficient compute accelerators
  on FPGAs
• Opportunity to build skills that bridge into
  ASIC flows
  , including RTL quality, test benching, and synthesis-readiness
• Mentorship from a team with expertise in
  hardware-software co-design
  , digital architecture, and early-stage prototyping