ASIC Engineer, Design Verification
Listed on 2026-01-12
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Engineering
Systems Engineer, Software Engineer, Electronics Engineer
ASIC Engineer, Design Verification
Meta is hiring an ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System on Chip (SoC) for data center applications.
As a Design Verification Engineer, you will be part of an agile team working with the best in the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub‑system from test‑planning, UVM‑based test bench development to verification closure. In addition to traditional simulation, you will use approaches such as Formal and Emulation to achieve a bug‑free design.
The role provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation, and Post‑Silicon teams toward creating a first‑pass silicon success.
$146,000/yr – $209,000/yr
ASIC Engineer, Design Verification Responsibilities- Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub‑system/SoC level verification.
- Develop functional tests based on the verification test plan.
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
- Debug, root‑cause, and resolve functional failures in the design, partnering with the Design team.
- Collaborate with cross‑functional teams (Design, Model, Emulation, Silicon validation) to ensure the highest design quality.
- Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools, and technologies from the industry.
- Bachelor’s degree in Computer Science, Computer Engineering, a related technical field, or equivalent practical experience.
- 6+ years of hands‑on experience in System Verilog/UVM methodology and/or C/C++ based verification.
- 6+ years of experience in IP/sub‑system and/or SoC level verification based on System Verilog UVM/OVM based methodologies.
- Experience with EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
- Experience with revision control systems like Mercurial (Hg), Git, or SVN.
- Experience with verification of ARM/RISC‑V based sub‑systems or SoCs.
- Experience in one or more of the following areas along with functional verification: SV Assertions, Formal, Emulation.
- Experience in developing UVM based verification environments from scratch.
- Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.
- Experience with IP or integration verification of high‑speed interfaces such as PCIe, RoCE, Ethernet, DDR, HBM.
- Experience with micro‑architectural performance verification.
- Experience verifying GPU/CPU designs.
- Experience with Design verification of Data‑center applications such as Video, AI/ML, and Networking designs.
- Experience working across and building relationships with cross‑functional design, model, and emulation teams.
- Track record of first‑pass success in ASIC development cycles.
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and Whats App further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers at Meta shape a future that reaches beyond the constraints of screens, distance, and even the rules of physics.
Meta is a proud Equal Employment Opportunity and affirmative action employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or any other legally protected characteristic. We also consider qualified applicants with criminal histories, consistent with applicable federal, state, and local law.
Meta participates in the E‑Verify program in certain locations, as required by law. We may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need assistance or accommodations due to a disability, please let us know at
Seniority levelNot applicable
Employment typeFull‑time
Job functionEngineering and Information Technology
Location:
Menlo Park, CA
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