Senior IC Design Engineer

Required

• Deep experience in IC design leading to production, production debug, testing support and yield enhancement
• Experience with RF system architectures, link budgets, trade-offs for key elements such as DC offset calibration loop, IIP2 calibration loop, AGC, etc.
• RF or analog circuit design for WiFi, LTE, TV or other high dynamic range systems
• Implementation experience in either 65nm or 40nm
• At least 7 years at a relevant comm IC house or IDM

• Experience with leading a team from design concept through project completion
• Lab and testing experience: spurious debug, noise testing, performance testing
• Customer-facing exposure: determining specifications, schedule, technical trade-offs

• LNA, Mixer, VGA, PA driver, IQ modulator Active filter design
• Active filter design, high speed op-amp, log limiter amplifiers, power detection PLL, integer/fractional loops, PFD
• PLL, integer/fractional loops, PFD, high speed divider circuits, VCO, loop filter, PLL system analysis, timing analysis, pre-scalers, High speed DAC design, above 10 bit, above 300
  
  MSPS
• High speed DAC design, above 10 bit, above 300
  
  MSPS High speed ADC design, (one of or all — pipeline
• High speed ADC design, (one of or all — pipeline, SAR and CTSD), above 10 bit, above 80
  
  MSPS

• McKinney, Texas (preferred)

• Start Date:
  
  Immediate
• Email resumes to:
• No calls. EOE.

Palma Ceia Semi Design announces Silicon-Proven IEEE 802.11ah HaLow Transceiver for Industry-Standard IoT Applications

Palma Ceia Joins Wi-Fi Alliance®