Field-Programmable Gate Arrays Engineer

Job Title:

Memory I/O Design Engineer

Location:

Boxborough, MA (100% Onsite)

Contract:

1 Year

Client: AMD

$45.00/hr - $50.00/hr

We are seeking a Memory I/O Design Engineer to join the High-Speed I/O design team responsible for developing and implementing DDR IPs. This role will primarily focus on SPICE simulations and System Verilog behavioral modeling, working closely with an established Analog/Mixed‑Signal (AMS) group including the supervisor, AMS manager, IP director, and core design team members.

• Scripting with TCL, Python, and Shell

• Run SPICE simulations for circuits such as Transmitters, Receivers (CTLE/DFE), DLLs, DACs, OpAmps, Comparators, and voltage regulators.
• Develop behavioral models of circuit characteristics using System Verilog.
• Build tools, write documentation, and define best practices.
• Contribute to developing design flows that improve execution efficiency and quality.

• Hands‑on experience with HSPICE or Spectre for circuit simulation.
• Data analysis & scripting using TCL and Python.
• Strong understanding of transistor‑level circuit analysis.
• Familiarity with Linux CLI and revision control systems (Perforce preferred).
• Strong communication and documentation skills.

• Knowledge of design verification flows.
• Ability to review and understand RTL or firmware code used in custom circuit implementations.
• Experience enhancing tool integrations and writing scripts for automation.

• Bachelor’s, Master’s, or PhD in Electrical Engineering or Computer Engineering.