Low Power Design Verification Engineer

Low Power Design Verification Engineer – AMD

Base pay range: $/yr - $/yr

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.
Together, we advance your career.

The focus of this role is to develop, execute, debug tests and methodologies for SoC low power features. You will work closely with the Architecture, IP/SoC Design, Physical Design Teams, and Product Engineers to achieve first pass silicon success.

Join us if you have passion for modern, complex processor and SoC architectures, digital design and verification. We are looking for a team player who has excellent communication skills and experience collaborating with engineers located in different sites/time zones. The ideal candidate for this role will possess strong analytical and problem solving skills, and are willing to learn and ready to take on challenges.

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Build the directed and random verification tests
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
• Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements

• SoC level ASIC verification experience
• Experience with multiple SoC tape‑outs taken to production
• Hands on experience of Low Power design and verification methodologies (e.g., UPF, power domains, multi‑voltage)
• NPU/AI processor knowledge
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in developing and using UVM based verification frameworks and test benches, processes and flows in both Linux and Windows environments
• Automating workflows in a distributed compute environment
• Experienced with Assembly, Verilog, System Verilog, C, C++
• Good understanding and hands‑on experience in the UVM concepts
• Good working knowledge of System
  
  C and TLM with some related experience
• Scripting language experience:
  Perl, Python, Ruby, Makefile, shell preferred

• Bachelors, Masters or PhD in Computer Science, Electrical Engineering or relevant fields

Location: Boxborough, MA

This role is not eligible for Visa Sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.