PCIe SubSystem Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

When you join AMD, you’ll be part of a team that delivers exciting products, offers professional growth, and encourages innovation and creativity at every stage of development.

AMD is looking for an experienced Design Verification Engineer to verify a leading edge PCIe Controller Design. In this role you will be given an opportunity to work on next‑generation technology that will be part of future AMD SOCs powering AI Training and Inference, Gaming Consoles, Servers and Personal Computers as well as Graphics Cards and VR sets. The team is responsible for verifying several critical blocks, interoperability of lower‑level IPs and the Sub System delivery to SoC.

The team is tasked with verifying a balanced architecture between power consumption and performance, delivering high‑complexity RTL code and Verification components, as well as creating advanced test benches using leading‑edge verification techniques.

A successful candidate will work with architects and fellow design and verification engineers. The candidate will be highly accurate and detail‑oriented, possessing strong communication, technical, leadership and problem‑solving skills. They can work well with cross‑functional teams, are skilled at driving tasks from start to completion with superior quality, and are flexible in working hours to accommodate colleagues in different time zones.

• Work on functional verification execution from test plan to verification sign‑off.
• Collaborate with architects and designers to understand the IP features.
• Write/implement/review test plans.
• Verify critical high‑speed digital designs using both coverage‑driven random and directed testing techniques as well as formal verification.
• Own some or all aspects of the verification flow from initial test planning to coverage convergence and sign‑off closure for one or more features and aspects of Sub System level IP interoperability.
• Build testbench components and develop test and sequence libraries, by applying object‑oriented programming verification techniques following UVM methodology.
• Conduct and participate in code reviews.
• Provide technical leadership, including block ownership from start to finish and verification sign‑off.

• Proven experience verifying commercially successful IPs, subsystems and/or SoCs.
• Strong ability to mentor and guide junior and senior engineers, a very effective team player, must have strong technical skills and provide a positive influence on team morale and culture.
• Must be expert in System Verilog, UVM.
• Proficient in object‑oriented programming, scripting (Ruby, Python, Perl), and low‑level programming languages.
• PCI Express, SATA, USB, Ethernet, Hyper Transport, DDR system architecture knowledge.
• Excellent knowledge of standard bus/interface protocols (AXI, AHB, AMBA, OCP, PIPE).
• Experience with simulation profiling, efficiency improvements, acceleration, HLS tools/process.
• Must be a self‑starter, able to drive independently and efficiently challenge time‑critical tasks to on‑time completion.
• Strong communication, time management, and presentation skills.

• Bachelor’s or Master’s degree in Computer Engineering/Electrical Engineering

Markham

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