Machine Learning ASIC Design Verification Engineer

Company:

Qualcomm Canada ULC

Engineering Group, Engineering Group > ASICS Engineering

QUALCOMM is the world’s leading developer of next-generation wireless and multimedia technology.

We are searching for an ASIC design verification engineer interested in developing world-class solutions for the next generation of AI/ML HW IP.

• • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• OR Master’s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

• Strong analytical and debugging skills
• Good working experience with C/C++
• Strong knowledge of Object Oriented Programming (OOP) concepts
• Hardware verification languages (HVL):
  System Verilog testbench (UVM), and/or SystemC
• Hardware description languages (HDL):
  Verilog and System Verilog
• Knowledgeable in one or more of the following disciplines is preferred:
  Display (Pixel processing/composition/compression, MIPI DSI, Display Port, HDMI etc.), Bus/interconnect (AHB, AXI)
• Strong knowledge of digital circuits and event-driven simulators
• Knowledgeable with Perl, Python, TCL, tcsh, and GNU Make
• Strong communication skills (written and verbal) to convey complex information to peers.
• Detailed oriented and be able to plan and prioritize tasks effectively.

• Prior experience delivering Verilog and/or System Verilog RTL
• Detail oriented with strong analytical and debugging skills
• Strong communication (written and verbal), collaboration, and specification skills
• Practiced working experience with some of the following concepts:
  • Clock domain crossing and reset architecture
  • Machine Learning HW development
  • FIFOs implementation
  • Bus implementation/verification techniques
  • Memory selection and control
  • High speed and low power design optimization
  • Bus interface protocols (AHB, AXI)
• Experience with some of the following: ul>
• Simulation and code coverage tools (VCS, Verdi, Modeltech/Questa, or Xcelium)
• Design rule and CDC checking (SVA assertions, Spyglass, 0-in, etc.)
• Scripting languages (PERL, Python, TCL, C, etc.)
• Power Intent and Analysis: UPF, CLP, PTPX, Power Pro
• Synthesis: DCG/NXT, FC
• Static Timing:
  Primetime
• Formal Verification:
  Conformal, Formality

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The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation  also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus).

In addition, our highly competitive benefits package is designed to support your success at work, at home, and r recruiter will be happy to discuss all that Qualcomm has to offer.

If you would like more information about this role, please contact Qualcomm Careers.