Timing & SDC Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE:

As a Timing / SDC Engineer, you will be responsible for developing and validating timing constraints (SDC) and performing static timing analysis (STA) for complex SoC or CPU designs. This role involves collaborating with RTL, physical design, and DFT teams to ensure timing closure across multiple modes and corners, while maintaining design quality and power efficiency. THE PERSON:
You are passionate about modern, complex processor architectures. You have deep experience in ASIC design, Synopsys design constraint (SDC) creation, and static timing analysis (STA). You are a collaborative team player with strong communication skills and a history of working across geographies and disciplines. You possess excellent analytical and problem-solving abilities, are eager to learn, and thrive in tackling complex design challenges

KEY RESPONSIBILITIES:

Timing Constraints Development:
Create and validate block-level and full-chip SDCs for functional and test modes. Develop methodologies for promoting block-level constraints to full-chip and vice versa. Static Timing Analysis (STA):
Perform STA sign-off for high-performance designs across multiple voltage and clock domains. Address setup/hold violations and optimize timing closure. Methodology & Flow Development:
Research and implement new timing and constraint validation methodologies. Automate timing checks and regression flows for efficiency. Cross-Team

Collaboration:

Work closely with RTL, physical design, and DFT teams to resolve timing issues. Mentor junior engineers on SDC development and STA best practices. Documentation & Reporting:
Generate timing budgets, clocking diagrams, and related documentation. Summarize timing analysis results and report progress to management.

PREFERRED EXPERIENCE:

Hands-on experience in ASIC design, SDC creation, and STA. Strong knowledge of timing constraints, clock groups, exceptions, and exclusivity. Proficiency with STA tools (Synopsys Prime Time, Cadence Tempus). Familiarity with synthesis tools (Design Compiler) and constraint validation tools (TCM, CCD). Strong scripting skills (Tcl, Python, Perl) for automation.

Experience with advanced process nodes (7nm or below). Understanding of multi-mode/multi-corner analysis, OCV/AOCV/POCV margining. Knowledge of low-power techniques and UPF/CPF flows.

Experience with hierarchical design and timing budgeting. Familiarity with ARM CPU STA or similar high-performance architectures. Exposure to IR drop analysis and physical implementation flows. ACADEMIC CREDENTIALS:
Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related field.

LOCATION:

Markham, ON #LI-IA1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection…