Principal Functional Verification Engineer; m​/f​/d

Staff / Principal Functional Verification Engineer (m/f/d)

Location:

Mannheim, Germany (Hybrid) or Villach, Austria (Hybrid)

Employment Type:

Permanent, Full-Time

Salary:
Competitive and negotiable

We are looking for an experienced Staff / Principal Functional Verification Engineer to join our team delivering high-performance on-chip network (NoC) solutions. You will develop and maintain UVM System Verilog verification environments, collaborate with design teams, and ensure high-quality, on-time product releases.

• Develop and maintain UVM System Verilog verification environments for NoC IP
• Define and execute functional verification plans
• Design and enhance verification test benches
• Debug complex design and verification issues
• Drive coverage closure and monitor regression runs
• Collaborate with design and cross-functional teams for successful product releases

• B.S./M.S. in Electrical Engineering, Computer Engineering, Physics
  , or related field
• 10+ years of relevant experience
• Strong expertise in UVM System Verilog and System Verilog Assertions
• Experience with Cadence Xcelium/vManager preferred
• HDL coding experience (Verilog/System Verilog/VHDL) a plus
• Scripting skills:
  Python, TCL, Bash
• Excellent English communication skills
  ;
  German a plus

• Flexible working hours and hybrid/remote options
• Competitive salary and career growth opportunities
• Team-oriented, supportive environment with regular events
• Workation option: up to six weeks per year

Locations:
Mannheim, Germany or Villach, Austria

If you are interested, please get in touch and send your CV to