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Physical Design Engineer

Job in Los Angeles, Los Angeles County, California, 90079, USA
Listing for: OpenAI
Full Time position
Listed on 2026-01-12
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Hardware Engineer, Electrical Engineering
Salary/Wage Range or Industry Benchmark: 125000 - 150000 USD Yearly USD 125000.00 150000.00 YEAR
Job Description & How to Apply Below

About the Team

OpenAI’s Hardware team designs the custom silicon that powers the world’s most advanced AI systems. From system-level architecture to custom circuit implementations, we partner closely with model and infrastructure teams to deliver performance, power, and efficiency breakthroughs across all layers of the stack.

About the Role

We are seeking a highly skilled Silicon Implementation Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our physical design team and is central to delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators.

In this role, you will:
  • Develop, build and own tools, flows and methodologies for physical implementation
  • Own physical implementation of floorplan blocks from floor planning to final signoff
  • Collaborate with RTL designers to drive optimal block implementation solutions
  • Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners
Qualifications
  • BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development
  • Demonstrated success in taping out complex silicon designs
  • Hands‑on experience with block physical implementation and PPA convergence
  • Strong coding experience with python, bazel, TCL
  • Strong experience building physical design tools, flows and methodologies
  • Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure.
  • Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation
Bonus
  • Experience with AI or HPC-focused chips
  • Experience with optimizing PPA for high performance compute cores
  • Hands‑on experience with top-level design methodologies

We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.

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