Lead QPU Design Engineer

About The Role and Team

Quantum Motion is a fast-growing quantum computing scale‑up based in London. We are developing quantum processors based on industrial‑grade silicon chips, with the potential to radically transform computing power in areas such as materials modelling, medicine, artificial intelligence and more.

Since 2021 our team has been listed every year in the “Top 100 Startups worth watching” in the EE Times, and our technology breakthroughs have been featured in The Telegraph, BBC and the New Statesman. Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co‑founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation.

We’re backed by a team of top‑tier investors including Bosch Ventures, Porsche SE, Sony Innovation Fund, Oxford Sciences Innovations, INKEF Capital and Octopus Ventures, and we have so far raised over £62 million in equity and grant funding.

We bring together the brightest quantum engineers, integrated circuit (IC) engineers, quantum computing theoreticians and software engineers to create a unique, world‑leading team, working together closely to maximise our combined expertise. Our collaborative and interdisciplinary culture is an ideal fit for anyone who thrives in a cutting‑edge research and development environment focused on tackling big challenges and contributing to the development of scalable quantum computers based on silicon technology.

Our team of 100+ is based in Oxford and London, with a centre of mass in our Islington lab.

We are hiring a Lead QPU Design Engineer to lead end‑to‑end design execution for silicon spin qubit quantum processor units (QPUs) and test vehicles, from concept through tapeout. This is a unique opportunity to work at the boundary between quantum physics and semiconductor engineering, exploring new device concepts while building industry‑standard infrastructure for manufacturability.

This is a hybrid hands‑on execution and team leadership role. You will personally implement critical work (layout or simulation, depending on your background) while defining standards, running reviews, and managing a complementary team.

We are open to candidates whose primary expertise is in layout or simulation. You must have working fluency in the other, enough to review critically and integrate effectively.

• Translate qubit architecture requirements into manufacturable physical designs: gateway layouts, bias networks, and multi‑qubit interconnects.
• Define connectivity/schematic capture and generate netlists for circuit simulation and LVS verification.
• Own tapeouts, including readiness reviews, verification, risk management.
• Execute critical design work in your domain (layout or simulation); review and integrate the other.
• Collaborate with experimentalists and the device modelling team to refine designs and device models based on fabrication constraints and simulation results.
• Define design workflows, standards, tool chains, and guide PDK and DFT development.
• Lead and mentor the QPU Design team.

• PhD or equivalent experience in EE, physics, or a related field.
• 8+ years in experimental hardware within research‑adjacent environments industry environments.
• Led hardware from concept through tapeout with personal accountability.
• Deep expertise in one domain with fluency in the other domain:
  • Layout‑first: custom physical design of block‑ and chip‑level layouts using Cadence Virtuoso or similar.
    • Hands‑on DRC/LVS/extraction.
    • Personally owned tapeouts.
    • Worked with sim teams, ran basic TCAD/EM, debugged layout via sim.
  • Simulation‑first: EM/electrostatic/circuit modeling using relevant tools such as Ansys (HFSS/Q3D), Keysight ADS, Cadence Spectre, Synopsys Sentaurus, or equivalent.
    • Validated models against measured data.
    • Iterated on layouts, understand best practices and DRC constraints, constructively critiqued layout decisions.
• Understanding of semiconductor device physics.
• Built processes, mentored engineers, and integrated across physics/sim/layout.