ASIC Design Verification

Job Description

Ensure the functional correctness, performance, and adherence to specifications for complex digital ASIC Core/IP designs. This role focuses on deep, unit, and core-level verification.

• Develop comprehensive Core Verification Plans based on the unit's micro-architecture and design specification.
• Design and implement reusable, robust verification environments using System Verilog/UVM.
• Test:
  Create and execute constrained-random and directed tests to achieve high functional and code coverage for the core unit.
• Debug:
  Analyze simulation results, debug complex failures, and collaborate with the design team to root-cause and fix issues.
• Automate:
  Develop and maintain scripts (Python/Perl) to enhance the verification flow and regression management.

• System Verilog/UVM expertise is mandatory.
• At least 7 years of hands‑on expertise.
• Strong grasp of digital logic design and verification methodologies.
• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems). Proven ability to work autonomously and demonstrate technical confidence when engaging with, and providing constructive feedback to, FE RTL design teams and CPU/IP micro‑architects.
• Proficiency with industry‑standard EDA simulation and debug tools.
• Solid abilities in debugging and root‑cause analysis.
• Experience with scripting (Python, Perl).
• Excellent written and verbal communication skills in English are required.

• Strong knowledge of CPU/Processor architectures (e.g., pipeline, cache, instruction sets, exceptions) like ARM, X86 or RISC‑V, is highly beneficial for verifying processor cores or complex IP blocks.