Senior Silicon Physical Design Engineer

Axelera AI is not your regular deep‑tech startup. We are creating the next‑generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. In just four years, we have raised $120 million, built a world‑class team of 220+ employees across 17 countries, launched our Metis™ AI Platform, and have a strong business pipeline exceeding $100 million.

Senior Silicon Physical Design Engineer – develop cutting‑edge multi‑core in‑memory compute SoCs. Responsible for all aspects from RTL to GDS: synthesis, floor planning, place and route, extraction, timing analysis, physical verification, EMIR signoff, formal verification; collaborate with architecture and RTL teams.

• Perform synthesis, floor planning, place and route, extraction, timing analysis, and physical verification.
• Constraint generation, timing analysis and optimisation.
• Execute clock tree synthesis (CTS) and custom clock‑building techniques.
• Integrate IPs including memories, I/Os, embedded processors, DDR, networking fabrics, and analog IPs.
• Utilise EDA tools such as Prime Time, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre.
• Develop automation scripts in Python, Tcl, Bash and contribute to flow development.
• Debug and solve technical challenges related to physical design.
• Collaborate with architecture, RTL, and verification teams.

• 10+ years of experience in Physical Design (RTL to GDS).
• Strong communication and teamwork skills.
• Expertise in all aspects of physical design.
• Hands‑on experience with leading EDA tools (Prime Time, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk, and Calibre).
• Proficiency in clocking techniques and CTS.
• Experience in IP integration across various domains.
• Strong scripting skills (Python and Tcl).Proven problem‑solving and debugging capabilities.
• Fluent in English (spoken and written).

• Experience in floor planning and top‑level integration.
• Knowledge of chip‑package‑board co‑simulation and packaging.
• Experience working with EDA vendors to resolve tool issues.
• Understanding of semiconductor device physics and multi‑domain design.

• Work from an Axelera AI office in Leuven (Belgium), Amsterdam or Eindhoven (Netherlands), Florence or Milan (Italy) or Bristol (UK) if you are based nearby.
• Fully remote from any European country (including the UK).
• Relocate with us to Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven).

Priority will be given to candidates based in Belgium or Italy.

Competitive compensation package with pension plan, extensive employee insurance, and company shares. An open culture that supports creativity and continual innovation; collaborative ownership and freedom with responsibility.

Mid‑Senior level

Full‑time

Engineering and Information Technology

Semiconductor Manufacturing

At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.