Engineering – FPGA Design​/Verification Engineer

Job Description:

The selected candidate will be responsible for ASIC & FPGA development on R&D program. This engineer will be a verification UVM (Universal Verification Methodology) expert.

• Experience verifying FPGA and/or ASIC designs including creating UVM verification environments, test benches, tests and coverage.
• Experience developing more affordable ways to automate and develop verification scripts to improve FPGA verification efforts.
• Experience with cross‑discipline collaboration with RTL Designers, Systems Architects, RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business growth, contributing to complex systems employing high speed networking concepts.
• Will need to have overall contribution to simulation, verification, integration & test of complex, high speed products.

The selected candidate will also provide support and technical direction to junior engineers.