Digital Verification Engineer

Location

Engineering | Linthicum Heights, Maryland, United States

Northrop Grumman is seeking a Staff Digital Verification Engineer for development of full‑custom digital and mixed‑signal superconducting processor circuits in Linthicum, MD. The role will utilize HDL (VHDL/Verilog) and HVL (System Verilog) with System Verilog Assertions (SVA) and Universal Verification Methodology (UVM). Strong written and oral communication skills are required.

• Develop and verify digital and mixed‑signal superconducting processor circuits.
• Implement HDL (VHDL/Verilog) and HVL (System Verilog) designs.
• Use System Verilog Assertions (SVA) and Universal Verification Methodology (UVM) for coverage‑driven verification.
• Collaborate with cross‑functional teams to meet design objectives.

• Bachelor’s degree in Engineering or a related technical discipline.
• 12 years of relevant experience (10 years with a technical MS; 7 years with a PhD).
• Proficient in HDL (VHDL/Verilog) and HVL (System Verilog).
• Experience with System Verilog Assertions (SVA) and Universal Verification Methodology (UVM).
• Knowledge of industry standard interfaces and coverage‑driven verification methodology.
• Object‑oriented programming skills.
• U.S. Citizen and able to obtain and maintain a security clearance.

• Advanced degree (MS or PhD).
• Experience with Mentor Graphics and/or Cadence verification tools and FPGA/ASIC design.
• Experience with scripting languages (Bash, Perl, Python, Tcl).
• Current security clearance.

Northrop Grumman provides a comprehensive benefits package including health plans, savings plans, paid time off, and additional benefits such as education assistance, training and development, 9/80 work schedule (where available), and more.

Northrop Grumman is an Equal Opportunity Employer and provides a diverse work environment. For our complete EEO and pay transparency statement, please visit