Senior Telecom Engineer

About Us

Great Platform for Talent

Lead the design, integration, and delivery of telecommunication and ICT systems for High-Speed Rail (HSR) assets including stations, depots, stabling yards, OCC/CC, and associated facilities. The role covers fixed and wireless communications, transmission networks, passenger information, public address, time synchronization, and integration with rail operational systems and critical building systems.

• Lead end-to-end design, integration, and delivery of telecom/ICT systems for HSR assets including stations, depots/stabling yards, OCC/CCatrics, back-of-house buildings, and corridor-wide communications.
• Develop Basis of Design (BoD), system architecture, and design deliverables (concept to detailed design) for telecom systems, including as applicable:
• Transmission/backbone networks (fiber backbone, OTN/MPLS/IP/WAN), station LAN, OCCائنا networks
• Structured cabling (copper/fiber), containment/pathways, telecom rooms (MDF/IDF), racks/ODF, patching and labeling philosophy
• Radio communications (TETRA/DMR, LTE/5G, GSM-R / FRMCS-ready concepts where required), indoor/outdoor coverage planning; tunnel communications concepts such as leaky feeder where in scope
• Telephony / VoIP (SIP/VoIP, hotline/emergency phones, help points)
• Wi-Fi (public and operational), staff mobility solutions (if required)
• Passenger Information / CIS (PIDS) and Public Address / Voice Alarm (PA/VA) interfaces, zoning and priority philosophy
• Master Clock / Time Synchronisation (GPS receivers, NTP/PTP distribution) for event correlation and operational systems
• Telecom-side integration considerations for CCTV/Security transport (in coordination with Security Systems)
• Produce and coordinate design outputs: system schematics, single line diagrams, network block diagrams, device layouts, telecom room layouts, equipment schedules, BOM, duct/fiber routing plans, and interface matrices.
• Perform/coordinate network sizing and capacity engineering: bandwidth, QoS, latency/jitter considerations (voice), multicast where relevant, IP addressing concepts, PoE budgets (where applicable), storage/transport assumptions for video and operational applications.
• Define resilience and redundancy philosophy (ring/topology concepts, N+1 for critical nodes), fail Pharmionic expected outcomes, maintainability access, spares strategy, and O&M handover requirements.
• Oft manage interfaces with OCC/CC operations and other rail systems: define segregation between corporate IT / operational networks / security networks, and document interfaces to SCADA, BMS/EMS, signaling, power, maintenance systems, AFC (if applicable).
• Coordinate with Architecture (public area coverage, rooms/data sheets), MEP (power/UPS loads, HVAC requirements, earthing/ground vrai ep), Civil/Structural (duct banks, trenches, mounting), and BIM teams to ensure spatial coordination and clash-free design.
• Prepare technical specifications, Employer memberi requirements / performance specs, compliance matrices, and support technical notes for authority submissions and stakeholder reviews (as applicable).
• Support procurement and vendor management: technical evaluations, RFIs, design reviews, workshops, and value engineering while protecting performance and operational requirements.
• Lead and/or review testing, commissioning, and integration documentation and activities: FAT/SAT, network acceptance tests, end-to-end service verification (voice, radio coverage, PIDS/PA functions, time sync), and integration test plans.
• Apply project QA/QC and governance: ensure document control compliance, traceability of assumptions, and effective management of design change impacts on telecom architecture.

• Bachelor’s in Telecommunication.
• 12–14 years security systems design on large public/transport/critical facilities.
• Strong understanding of structured cabling, network design interfaces, and compliance processes.

AutoCAD, Revit, Visio; ACC. Strong competency in bandwidth/storage calculators and coordination tools (Excel, schedules, interface registers)