DFT Engineer

A forward thinking Swiss fabless semiconductor company based in Lausanne is seeking to bolster their team with a talented DFT Engineer.

• Design and implement DFT architectures, including hierarchical scan and MBIST insertion, scan compression, and boundary scan (BSD)
• Generate ATPG patterns, perform fault coverage analysis, and drive convergence to high coverage targets
• Execute timing‑aware pattern simulations, define test‑mode timing constraints, and analyze timing reports
• Develop cycle‑accurate functional test patterns using IJTAG methodologies
• Collaborate closely with test and production engineering teams to support silicon bring‑up, debug test issues, and resolve silicon failures

• Minimum 5 years of hands‑on DFT experience, including implementation, test pattern development, leaf and simulation for complex designs
• Proven expertise with IJTAG methodologies, hierarchical MBIST and scan insertion, and scan compression techniques
• Strong experience in ATPG for multiple fault models, coverage analysis, and timing‑aware debug
• Proficiency with industry‑standard DFT, timing, and simulation EDA tools, with working knowledge of System Verilog
• Excellent debugging, scripting, and communication skills, with a proactive, collaborative mindset

If this role is of interest please apply directly on Linked In or send a copy of your CV to

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