Digital Verification Lead Engineer - SerDes

Senior Consultant | Blockchain/Web3, Semiconductor, Software Engineering

We are partnered with a specialist semiconductor company delivering complex high-speed signaling and interconnect solutions. They are looking for an experienced Digital Verification Lead Engineer to take technical ownership of project verification, lead multi-site teams, and drive methodologies across complex designs.

This is a permanent position based in Lausanne, Switzerland (it is also possible to work from offices in the UK, Germany, or Denmark).

• Act as the verification lead on complex digital projects, providing technical leadership and mentoring to the team.
• Prepare comprehensive design verification plans based on design specifications.
• Plan, schedule, assign, and track tasks for multi-site team members, coordinating external subcontractors as needed.
• Develop advanced design verification methodologies and implement standard debug flows.
• Drive Metrics-Driven Verification (MDV), focusing on verification planning and efficient coverage closure.
• Maintain the verification environment, participate in design reviews, and actively track and close design bugs.
• Utilize the latest techniques, including constrained random test bench development and simulation environments.

• Experience in leading and managing a team across multiple sites.
• Proven track record in verifying complex designs (preferably in high-volume applications).
• Extensive digital verification background with some UVM (Universal Verification Methodology) experience.
• Deep understanding of simulation and verification environments, including debugging and Gate Level Simulation (GLS) flows.
• Strong knowledge of Metrics-Driven Verification and test bench development using the latest methodologies.
• Skilled in scripting techniques for regression setup and management.
• Familiarity with Ser Des and high-level protocols (e.g., PCIe, USB, DP) is advantageous.

Keywords: Digital Verification Lead / UVM / Constrained Random / Coverage Closure / Metrics-Driven Verification / Ser Des / PCIe / USB / Design Verification Plan / Technical Leadership / Gate Level Simulation / Debugging / Semiconductor / Multi-Site Management / ASIC / Verification Methodology

If you are interested in this Digital Verification Lead Engineer position, please send a copy of your CV to

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Seniority level: Mid-Senior level

Employment type: Full-time

Job function: Engineering and Design

Industry: Semiconductor Manufacturing