Formal Verification Engineer

Principal Consultant | Software Engineering, AI & CV/ML, Semiconductors & Electronics

European Tech Recruit is working closely with a leading semiconductor company based in Lausanne, who are looking for a talented Formal Verification Engineer to join their team.

This role can also be available working out of their Reading (UK), Northampton (UK) or Dortmund (Germany) offices.

Responsibilities as Formal Verification Engineer
:

• Develop formal verification methodologies and best practices.
• Participate in RTL design reviews.
• Prepare design verification plan based on design specifications.
• Document results and coverage metrics for formal sign-off.
• Plan and schedule assigned projects for timely completion.
• Maintain design verification environment and track & close design bugs.

Requirements:

• 5+ years’ experience in the semiconductor industry.
• Proven track record in verifying complex designs (preferably in high volume applications) – FPGA or ASIC.
• Skilled in trade‑offs between quality and schedule.
• Good scripting techniques (Python, Perl or TCL for automation), regression setup & management.
• Deep understanding of Formal Verification technologies.
• Strong knowledge of metrics‑driven verification (incl. test planning and coverage closure).
• Proficiency in temporal logic assertion‑based languages such as SVA or PSL.
• Knowledge of traditional simulation‑based verification methodologies (a plus).
• Working with RTL design engineers to develop a formal micro‑architecture specification.
• Familiarity with Ser Des and high‑level protocols (e.g., PCIe, USB, DP) would be advantageous.
• Delivered reusable and optimised formal models and verification codebases to improve efficiency across projects.

If this role is of any interest please apply directly on Linked In or send a copy of your CV to

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• Mid‑Senior level

• Full‑time

• Engineering, Information Technology, and Other

• Semiconductor Manufacturing, Computer Hardware Manufacturing, and Software Development