Digital Verification Lead

I’m seeking a Digital Verification Lead to join an innovative, deep-tech AI company that is a recognised leader in its field. You will join an established Verification group and support with Verification strategies across multiple sites in the next phase of growth. This role is based in Lausanne.

• Act as verification lead on projects
• Provide technical leadership & mentoring
• Prepare design verification plan based on design specifications
• Plan and schedule projects, assign and track tasks for team members
• Develop design verification methodologies and implement standard debug flows
• Participate in design reviews
• Maintain design verification environment and track & close design bugs
• Utilise the latest techniques, tools, and technologies for design verification activities

• Good scripting techniques, experience with regression setup & management
• Deep understanding of simulation and verification environments, including debugging techniques.
• Experience with Gate Level Simulation flows and debug
• Strong knowledge on Metrics-driven verification
• Experienced with test bench development using the latest methodologies

• 7+ years’ experience in the semiconductor industry
• Experience in leading and managing a team across multiple sites
  
  Proven track record in verifying complex designs
• Skilled in trade-offs between quality and schedule
• Experience in constrained random test bench development
• Familiarity with Ser Des and high-level protocols (e.g., PCle, USB, DP) would be advantageous
• Extensive digital verification background with some UVM experience
• Coordinate and oversee external sub-contractors to scale up verification workloads

• Competitive base salary
• Pre-IPO stock options
• Opportunity to contribute to cutting-edge AI and semiconductor innovation

For more information on this role or others, please contact Jordan Browne for more information.