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Formal Verification Engineer - Advanced RTL

Job in 1001, Lausanne, Canton de Vaud, Switzerland
Listing for: European Tech Recruit
Full Time position
Listed on 2026-01-12
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 CHF Yearly CHF 80000.00 100000.00 YEAR
Job Description & How to Apply Below

Formal Verification Engineer

We are partnered with a specialist semiconductor company delivering complex high-speed signaling and interconnect solutions. They are seeking a Formal Verification Engineer to establish and implement formal methodologies for sign-off on advanced RTL designs.

This is a permanent position based in Lausanne, Switzerland (it is also possible to work from offices in the UK, Germany, or Denmark).

Key Responsibilities
  • Develop and implement Formal Verification (FV) methodologies and best practices for design sign-off.
  • Prepare comprehensive design verification plans based on design specifications.
  • Document results and coverage metrics for formal sign-off.
  • Plan and schedule assigned projects and maintain the formal verification environment.
  • Work with RTL design engineers to develop formal micro-architecture specifications.
  • Deliver reusable and optimized formal models and verification codebases to improve efficiency.
  • Participate in RTL design reviews and actively track and close design bugs.
Key Requirements
  • Proven track record in verifying complex ASIC or FPGA designs (preferably in high-volume applications).
  • Deep understanding of Formal Verification technologies.
  • Proficiency in temporal logic assertion-based languages such as System Verilog Assertions (SVA) or PSL.
  • Strong knowledge of Metrics-Driven Verification (test planning and coverage closure).
  • Strong understanding of instruction-set architectures, interrupt handling, and bus architectures.
  • Proficiency in scripting for automation (Python, Perl, or TCL).
  • Experience with Cadence Jasper Gold and VManager is desirable.
Contact

If you are interested in this Formal Verification Engineer position, please send a copy of your CV to .

Seniority Level

Mid-Senior level

Employment Type

Full-time

Job Function

Engineering and Design

Industries

Semiconductor Manufacturing

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