DFT Engineer Speed​/Semiconductors

Overview

We are partnered with a specialist semiconductor company focused on delivering breakthrough high-speed signaling technology and advanced interconnect solutions. They are looking for a resourceful DFT Engineer to join their team in Switzerland to drive hierarchical implementation, pattern generation, and post-silicon bring-up for complex, high-performance designs. This is a permanent position based in Lausanne, Switzerland.

• Execute hierarchical MBIST and scan insertion, as well as Boundary Scan (BSD) implementation.
• Perform ATPG pattern generation and comprehensive coverage analysis to converge on high-coverage metrics.
• Conduct gate-level pattern simulations with timing to ensure robust test silicon.
• Define test mode timing constraints and analyze timing reports to achieve timing closure.
• Develop cycle-accurate functional patterns utilizing IJTAG (IEEE 1687) methodologies.
• Support test and production engineering teams during device bring-up and debug at both probe and final test stages.
• Actively investigate and resolve post-silicon hardware issues.

• 5+ years of dedicated DFT experience, covering implementation, test pattern development, and simulation.
• Proven track record of contributing to DFT solutions for complex, high-performance designs.
• Deep experience with hierarchical MBIST and scan insertion, including scan compression methodologies.
• Strong expertise in ATPG pattern generation for various fault models and driving fault coverage closure.
• Hands-on experience with IJTAG methodologies.
• Proficiency with industry-standard EDA tools for DFT, timing analysis, and simulation.
• Strong debugging capabilities, particularly in timing-annotated simulations.
• Solid knowledge of System Verilog and scripting skills for flow automation.

Keywords: DFT Engineer / Design for Test / MBIST / ATPG / Scan Insertion / Scan Compression / BSD / Boundary Scan / IJTAG / IEEE 1687 / Pattern Generation / Timing Closure / Fault Coverage / Silicon Debug / Device Bring-Up / System Verilog / Semiconductor / High-Speed Interconnect / Lausanne / Switzerland / ASIC Design

If you are interested in this DFT Engineer position, please send a copy of your CV to

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