Principal​/Senior Principal FPGA​/ASIC Verification Engineer

Position: Principal / Senior Principal FPGA/ASIC Verification Engineer

Relocation Assistance

Relocation assistance may be available

Clearance Type

Polygraph

Travel

Yes, 10% of the Time

Description

We are seeking digital verification engineers for our development of full-custom digital and mixed signal circuits. Must be proficient in HDL (VHDL/Verilog) and HVL (System Verilog). Experience with System Verilog Assertions (SVA) and Universal Verification Methodology (UVM) is required. Successful candidates will have familiarity with a coverage-driven verification methodology from planning through closure as well as knowledge of industry standard interfaces.

Experience with object-oriented programming languages and concepts is also required. Must have strong written and oral communication skills.

Location

100% onsite in Linthicum, MD OR Annapolis Junction, MD

Basic Qualifications Principal Digital Verification Engineer

• Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 5 years of relevant experience (3 years with technical MS; 0 years with PhD). Experience in HDL (VHDL/Verilog) and HVL (System Verilog).
• Experience with FPGA or ASIC.
• Knowledge of Universal Verification Methodology (UVM).
• Experience with scripting languages (Bash, Perl, Python, Tcl).
• Familiarity with Linux OS.
• Familiarity with a coverage driven verification methodology from planning through closure.
• Knowledge of industry standard interfaces.
• Experience with object-oriented programming languages and concepts.
• Must be a US Citizen and must have or be able to obtain and maintain a Top Secret/SCI security clearance with Polygraph.

Basic Qualifications Senior Principal Digital Verification Engineer

• Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 8 years of relevant experience (6 years with technical MS; 3 years with PhD). Experience in HDL (VHDL/Verilog) and HVL (System Verilog).
• Experience with FPGA or ASIC.
• Knowledge of Universal Verification Methodology (UVM).
• Experience with scripting languages (Bash, Perl, Python, Tcl).
• Familiarity with Linux OS.
• Familiarity with a coverage driven verification methodology from planning through closure.
• Knowledge of industry standard interfaces.
• Experience with object-oriented programming languages and concepts.
• Must be a US Citizen and must have or be able to obtain and maintain a Top Secret/SCI security clearance with Polygraph.

Preferred Qualifications Principal / Senior Principal Digital Verification Engineer

• Advanced Degree either MS or PhD.
• Active Top Secret/SCI security clearance with Polygraph.
• Experience with Mentor Graphics and/or Cadence Verification tools - FPGA/ASIC Design experience.

Salary

Primary Level Salary Range: $ - $

Secondary Level Salary Range: $ - $

EEO Statement

Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit  U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.

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