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Analog Design Engineer

Job in Irvine, Orange County, California, 92713, USA
Listing for: Celero Communications
Full Time position
Listed on 2026-02-28
Job specializations:
  • Engineering
    Systems Engineer, Electrical Engineering, Electronics Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 150000 - 250000 USD Yearly USD 150000.00 250000.00 YEAR
Job Description & How to Apply Below

Are you an Analog Design Engineer, Principal who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology powering next generation AI? We are looking for an Analog Design Engineer – someone who is excited to join a fast-growing Start-Up Company growing a group of diverse individuals responsible for handling high-speed mixed-signal circuit designs!

Candidate will have the opportunity to architect and design circuits for high performance transceivers and other critical analog functions.

What You Will Do:
  • High speed analog circuit design, such as high-speed broadband amplifiers (VGA, CTLE, DRV, etc.).
  • Clock generation and distribution (VCOs, PLL, clock distribution, etc)
  • New techniques for the development of next generation optical transceiver
  • Design of custom passive components, from concept to silicon implementation
  • Supervise analog layouts within advanced process nodes
  • System verification and circuit design spec creation
  • Silicon bring-up, debug and support
  • Team communication and documentation
What You Will Bring:
  • Master’s degree and/or PhD (preferred) in Electrical Engineering or related fields with 5+ years of experience.
  • Should have strong analog design fundamentals and experience in designing analog circuit blocks for broadband amplification, clock generation and distribution, and/or fundamental analog blocks.
  • Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must
  • Experience with electromagnetic simulation tools (EMX, Momentum, HFSS or other)
  • Knowledge of the fundamentals on electromagnetism, lump models and high frequency design
  • Good understanding of analog layouts in Fin Fet and its effect on high-speed designs is a plus
  • Experienced in lab chip bring-up and debugging efforts is a plus
  • Strong communication and documentation skills
Salary Range

$150,000 - $250,000 Base Annually

The final offer will be determined based on job-related skills, experience, qualifications, and location.

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