Senior RTL Design Engineer

Principal RTL Design Engineer / Senior FPGA Design Engineer Needed for Leading Telecom Company!

2 days ago, Be among the first 25 applicants.

$/yr - $/yr

• A competitive base salary between $150,000 and $250,000!
• 401(k) plan
• Medical, dental and vision coverage
• PTO/vacation
• Flexible work from home policy on Tuesdays and Fridays

As a Senior RTL Engineer / Lead FPGA Design Engineer on our team, we are looking for a talented Staff RTL Design Engineer / Principal FPGA Design Engineer to lead our RTL and FPGA design initiatives.

• Bachelor of Science degree in Electrical Engineering, Computer Science, or a related field.
• Minimum 3 years of demonstrated experience in RTL design and FPGA implementation; advanced degree (MS or PhD) is a plus.
• Demonstrated experience with fixed‑point binary arithmetic and digital signal processing designs.
• Deep knowledge of RTL design fundamentals using Verilog and System‑Verilog.
• Proven expertise working with front‑end RTL design tools, FPGA synthesis, timing closure, multi‑clock‑domain, and/or high‑utilization FPGA designs.
• Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.

Not Applicable

Full‑time

Engineering and Information Technology

IT Services, IT Consulting, and Software Development

Jobot is an Equal Opportunity Employer. We provide an inclusive work environment that celebrates diversity and all qualified candidates receive consideration for employment without regard to race, color, sex, sexual orientation, gender identity, religion, national origin, age (40 and over), disability, military status, genetic information or any other basis protected by applicable federal, state, or local laws. Jobot also prohibits harassment of applicants or employees based on any of these protected categories.