Mixed-Signal Verification Engineer

Job Title: Mixed-Signal Verification Engineer
Location: Switzerland, UK, Germany, Denmark (Hybrid)
Industry: Semiconductor / High-speed interconnect / Ser Des

A high-growth semiconductor scale-up is looking for an experienced Mixed‑Signal Verification Engineer to support the verification of high‑speed, energy‑efficient chip‑to‑chip communication technologies. This position offers the opportunity to work on advanced Ser Des architectures within an innovative, fast‑moving technical environment.

• Verify analog and mixed‑signal blocks related to high‑speed Ser Des designs
• Debug and communicate design bugs with the design team
• Develop and improve verification methodologies in collaboration with internal teams and EDA vendors
• Document and track verification tasks, issues, and methodology progress

• Strong scripting capabilities
• Solid understanding of fabrication processes, process corners, simulation, and verification environments
• Expertise in electrical and discrete test benches with focus on runtime optimization
• Strong knowledge of simulation tools and debugging techniques
• Experience with revision/version control systems
• Excellent communication and reporting skills

• Minimum 10 years’ experience in digital, analog, or mixed‑signal verification
• Testbench creation, module connectivity, and electrical/discrete partitioning expertise
• Knowledge of UDN, wreal, and compile/elaboration debugging
• Behavioural modelling experience and familiarity with analog building blocks
• Experience with constrained‑random verification environments
• System Verilog Assertions expertise
• Hands‑on experience with Cadence tools including APS, Spectre
  
  X, Xcelium, Ocean Script, and Virtuoso (schematic, assembler, AMS)
• Exposure to Specman or System Verilog UVM preferred
• Experience with high‑speed communication systems such as Ser Des is highly desirable

Degree in Electrical Engineering or a related discipline

If you are suited and interested, please send your updated CV to