Process Integration Engineer, APTD

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Advanced Packaging Technology Development (APTD) department at Micron Technology is at the forefront of innovation, driving the advancement of memory and storage interconnects and packaging solutions that transform how the world uses information. Micron is dedicated to developing innovative processes and technologies that enable the creation of next‑generation semiconductor products which drive the AI revolution. By collaborating closely with our global R&D, equipment and materials suppliers, and manufacturing teams, we ensure the efficient development, transfer and implementation of new technology nodes, maintaining Micron's leadership in the industry.

As a Staff Process Integration Engineer in APTD at Micron, you will own the end‑to‑end integration of next‑generation package architectures: 2.5D, 3D stacking, HBM memory integration, and hybrid bonding. You’ll lead new advanced packaging technology development, technology transfer, design DOEs, analyze yield and reliability, and coordinate across device, design, process, equipment, test, and manufacturing teams to deliver high performance multi‑die technology.

The role will operate in a cleanroom environment in full gowning, adhering to EHS/cleanroom protocols. The role may require occasional travel to TD sites in Asia for integration development and transfer support.

• Own package‑level process integration across 2.5D/3D flows (wafer‑to‑wafer, chip‑to‑wafer, advanced interconnects), defining specs and process windows that meet high performance targets for HPC/AI products
• Develop and integrate semiconductor manufacturing processes. Design, optimize, and implement fabrication flows that seamlessly integrate multiple steps, including lithography, etch, deposition, diffusion, CMP, and thin films, into cohesive production processes.
• Analyze yield, performance, and defect data to root‑cause process weaknesses, yield issues, and tool variances; employ SPC and advanced analytics.
• Lead technology transfer from TD to TD and HVM, establishing mask rules, materials, tool readiness, baseline qualification, and technology validation plans.
• Design and execute experiments (DOEs) on bonding, underfill, molding, stacking, and integration steps. Apply SPC to para metrics and yield detractors, validate new materials, design rules to improve yield and device performance, and close the loop with corrective actions.
• Manage hybrid bonding (Cu‑Cu + dielectric) integration. Set surface prep, planarity, and alignment requirements. Qualify W2W/C2W flows and track defectivity and reliability.
• Optimize underfill, TC bonding windows, and pillar/bump geometries for high‑I/O assemblies.
• Co‑optimize TSV/interconnect routing and thermal paths to meet bandwidth/latency targets, aligning package floor plans with chiplet partitioning.
• Predict and mitigate wafer/die warpage engineering via modeling, cure‑shrinkage controls, and material/process levers; validate with inline metrology.
• Leverage metrology and inspection skills to deploy SAM, IR microscopy, and emerging XRD warpage mapping to correlate processes, defects, and reliability.

• BS or MS in Materials/Chemical Engineering
• 6+ years in semiconductor technology development with cleanroom experience
• Hands‑on knowledge of advanced interconnects and bonding flows
• Proficiency in DOE/SPC and data analysis (JMP/Minitab/Python) with demonstrated root‑cause problem solving and yield improvement
• Experience with metrology; SAM, X‑ray/CT, IR, warpage profilers (shadow moiré/DIC)
• Strong communication and technical writing skills with the ability to lead cross‑functional teams and drive action in fast‑paced environments
• Direct experience with hybrid bonding integration and reliability (W2W/C2W)
• Warpage modeling and inline correlation experience

As a world leader in the semiconductor industry,…