Pre-Silicon Validation Engineer; Mixed Signal

Pre-Silicon Validation Engineer (Mixed Signal)

Contract

USM Business Systems Inc. is a quickly developing worldwide System Integrator, Software and Product Development, IT Outsourcing and Technology assistance supplier headquartered in Chantilly, VA with off-shore delivery centers in India. We offer world-class ability in giving most astounding quality and administrations through industry best practices planned to convey remarkable worth to our customers.

Utilizing our industry knowledge, administration service offering expertise and innovation abilities, we distinguish new business and innovation slants and create answers for help customers around the globe, giving top of the line solid and practical IT benefits which are cost effective services.

Established in 1999, the organization has corner qualities in building and dealing with a Business Oriented IT environment with rich involvement in technology innovation, ERP and CRM counselling, Product Engineering, Business Intelligence, Data Management, SOA, BPM, Data Warehousing, SharePoint Consulting and IT Infrastructure. Our other offerings include modified solutions and administrations in ERP, CRM, Enterprise architecture, offshore advisory services ,e-commerce, Social , Mobile, Cloud, Analytics (SMAC) and Dev Ops.

USM, a US ensured Minority Business Enterprise (MBE) is perceived as one of the fastest developing IT Systems Integrator in the Washington, DC zone. Most as of late, USM was positioned #9 on the rundown of the Top administrations organizations in the DC Metro Area – Washington Business Journal (2011). We are a project-driven firm that reliably meets the IT needs of our State and Government customers through development and business keenness.

• Functional validation of products with both analog and digital components in them using digital and mixed signal simulation tools.
• Defining and developing necessary validation infrastructure tests, checkers and occasional scripting in Perl or Unix shell to execute the validation plans to ensure functional correctness of the design.
• Read and interpret technical specs and create high quality technical documentation.
• Understanding DUT specifications, digital logic and analog circuit implementation, defining validation strategy, creating test plans.
• Document validation plan and create appropriate software/content to execute to the plan.

• Must have either a BS or MS in Electrical Engineering, Computer Engineering or Electrical and Computer Engineering.
• 2 years experience with basic analog, mixed signal circuits.
• 2 years experience with digital logic design and simulation using Verilog/VHDL.
• 1 year experience with high speed I/Os like DDR, PCI‑express, USB or similar IO interfaces.
• 6 months experience with computer architecture.
• 6 months experience with scripting languages like Perl and/or Shell.
• 6 months experience with circuit simulation tools like Pspice and application of circuit analysis concepts.
• 2 years experience with UNIX or Linux.

• 6 months+ experience with Verilog‑A/VHDL‑A/AMS and mixed signal simulation tools like Cadence AMS, Mentor ADMS and/or their equivalent.
• 6 months+ industry experience in SOC/ASIC verification.
• 6 months+ experience in post‑SI debug and validation.
• Working knowledge of C/C++/System C and other high level languages.

If my requirement matches your resume, then please do reply on my email  
lakshmip@usmsystems(dot) com or can directly call me on