CPU Physical Design Engineer

Do Something Wonderful! Intel puts silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world‑changing technology that enriches the lives of everyone on earth. If you have a big idea, let's do something wonderful together.

The role’s responsibilities include (but are not limited to):

• Perform physical design implementation of custom CPU designs from RTL to GDS to create a design database ready for manufacturing.
• Conduct all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conduct verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyze results and make recommendations to improve current and future CPU microarchitectures, collaborating closely with logic, circuit, architecture, and design automation teams.
• Possess CPU‑specific expertise in structural and physical design, physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
• Work intimately with industry EDA vendors to build and enhance tool capabilities for high‑speed, low‑power synthesizable CPUs.
• Optimize CPU design to improve product‑level parameters such as power, frequency, and area.
• Participate in the development and improvement of physical design methodologies and flow automation.

Minimum qualifications:

• Bachelor’s degree in Computer/Electrical Engineering or related field with 8+ years of relevant experience.
• Master’s degree in Computer/Electrical Engineering or related field with 6+ years of relevant experience.
• PhD in Computer/Electrical Engineering or related field with 5+ years of relevant experience.

Must have experience in some or most of the following:

• Synthesis, Placement (PnR), Routing, CTS (clocks), Post‑Route Optimization, Verification and Sign‑off, Prime Time, Timing ECOs.

Preferred qualifications:

• Strong experience through multiple tape‑in cycles and a senior team contribution.
• Experience in physical design EDA tools, Perl and Tcl programming, low‑power and high‑performance design principles, familiarity with Verilog and CPU architecture.

Experienced Hire

Shift 1 (United States of America)

US, Texas, Austin

US, Oregon, Hillsboro

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, cores, and critical IPs from architecture to manufacturing readiness.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

We offer a total compensation package that ranks among the best in the industry, including competitive pay, stock bonuses, and benefits such as health, retirement, and vacation.

$ – $ USD

This role will require an on‑site presence. Job posting details (such as work model, location or time type) are subject to change.

Mid‑Senior level

Full‑time

Engineering and Information Technology

Semiconductor Manufacturing