Senior Engineer II-Verification

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values;

we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Microchip is seeking a highly skilled and experienced Senior Verification Engineer to join the Advanced Engineering Services team at our Fab 4 facility in Gresham, Oregon. The successful candidate will be responsible for leading the development and implementation of comprehensive verification plans to ensure optimal functionality of our manufactured devices.

• Develop verification test plans from design specifications.
• Build verification environments for chip/module level designs using System Verilog with UVM.
• Develop test cases using transaction based checkers to execute verification test plans.
• Manage and launch regressions using Cadence tools such as Verisium Manager and Xcelium Simulator.
• Interpret simulation results using tools such as Simvision to root cause discrepancies between expected and simulated results in collaboration with the design team.
• Generate and analyze code and functional coverage to ensure adherence to the test plan.
• Promote and apply advanced verification techniques including constrained random generation, functional coverage, assertions, and formal verification.
• Work with CAD team to resolve tool related issues and provide test cases, as required.

• MS degree in EE/CE with 5+ years of industry experience or B.S. degree in EE/CE with 7+ years of industry experience preferably in ASIC or FPGA environments.
• Proficient in HDL languages System Verilog, Verilog and VHDL.
• Apply UVM based verification using coverage driven verification techniques.
• Hands‑on experience with assertion‑based verification (ABV), including writing and debugging System Verilog Assertions (SVA).
• Experience with formal verification and assertion analysis tools such as Fishtail, Jasper Gold, or similar.
• Familiarity with the Linux compute environment.
• Excellent analytical and problem‑solving skills.
• Ability to clearly express complex design concepts and simulation results, both verbally and in written form.
• Proactive and able to work independently or as part of a team.
• Experience with using scripting languages (Python, Perl, Tcl) for automation.

• Object Oriented programming.
• Understanding of ASIC designs and verification methodologies.
• Domain Expertise: AHB, AXI, PCIe.
• Experience with additional simulation tools (e.g., VCS, Model Sim).

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We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In…