Staff Engineer - Logic Synthesis & Timing Closure

A leading semiconductor company located in Greenlawn, NY, is seeking a Staff/Senior Staff Engineer specializing in Logic Synthesis and Static Timing Analysis. The ideal candidate will have 8-14 years of experience, strong expertise in ASIC design, and proficiency with EDA tools such as Synopsys Design Compiler. Responsibilities include logic synthesis, timing analysis, and collaboration with cross-functional teams. You'll thrive in a flexible, inclusive environment that promotes career advancement and innovation.

Join us to shape the future of technology and make impactful contributions.
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