IC Layout Design Engineer

Welcome to Canova Tech, headquartered in Italy, where precision and innovation converge in the art of integrated circuit design. Our expertise in crafting both analog and digital circuits sets global standards and empowers industry leaders worldwide. At Canova Tech, each project is approached with a unique blend of meticulous craftsmanship and advanced technology, inspired by the artistry of neoclassical sculptor Antonio Canova.

Our medium is silicon, and our tools are cutting‑edge, ensuring that every chip embodies system efficiency and architectural excellence.
Join us in exploring ‘The Art of Silicon Sculpting.’ Here, engineering transcends traditional boundaries, and each circuit is not just a component but a masterpiece, harmonizing the legacy of the past with the innovations of the future.
We are seeking a IC Layout Design Engineer to join our innovative team. This role involves collaborating with circuit design teams to create complex analog layouts in BCD/CMOS/FinFET technologies. The position emphasizes quality assurance through design verification tools and requires a strong understanding of layout practices and CAD tools. Experience in FinFET technologies is definitely a plus.
Responsibilities   Collaborate with circuit design teams to plan and schedule work.
Negotiate layout trade‑offs to build complex analog layouts.
Recognize and correct failure‑prone circuit and layout structures.
Run design verification tools to ensure quality at all levels of chip design.
Interpret LVS, DRC, and ERC reports to expedite layout completion.
Meet engineering specifications by working closely with circuit design teams.
Utilize advanced CAD tools and mask design knowledge to deliver robust layouts.
Seniority level   Entry level

Employment type

Full‑time
Job function   Engineering and Information Technology
Industries   Semiconductor Manufacturing
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