Display Defect Metrology Engineer, Raxium

Display Defect Metrology Engineer, Raxium

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• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience.
• 2 years of experience working in an optoelectronics test or display metrology engineering team.
• Experience in leading edge technology of semiconductor engineering.
• Experience in data analysis.

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field (e.g., Optics, Sensors, Audio/DSP).
• 2 years of experience in software development or engineering.
• Understanding of statistical process control and improvement implementation.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

The US base salary range for this full-time position is $126,000-$181,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

• Identify flaws and issues with hardware components. Solve and analyze key issues, risks, or trade‑offs, and address common hardware failures by suggesting corrective solutions.
• Collaborate cross‑functionally to optimize hardware performance under established design constraints. Be responsible for meeting performance requirements of a complex hardware product or subsystem.
• Utilize inspection tools and data analysis techniques to proactively identify and address potential yield issues.
• Collaborate and drive equipment vendors for defect metrology tools to improve and optimize applications based on development requirements.
• Establish and maintain appropriate control charts and sampling plans for effective defect monitoring, Measurement System Analysis (MSA) and process control.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law.

If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

• Not Applicable

• Full‑time

• Other, Information Technology, and Engineering
• Information Services and Technology, Information and Internet