Senior Physical Design Engineer

Principal or Staff IP Integration Engineer
- Full-Time - Role Description

This is a full‑time on‑site role based in Fort Collins, CO, OR San Jose for a Senior Physical Design Engineer
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The Senior Physical Design Engineer will work on various stages of physical design, including implementation, optimization, and verification.

The responsibilities include collaborating with cross‑functional teams to integrate IPs, conducting timing analysis, power optimization, and performing physical verification to ensure design quality and compliance. The role will also involve developing and refining design methodologies to meet project delivery timelines.

• Proficiency in Physical Design processes, including floor planning, placement, routing, and timing closure.
• Strong experience in Physical Verification, including DRC (Design Rule Checking) and LVS (Layout Versus Schematic) tools.
• Knowledge in Logic Design and RTL Design, including synthesis and timing analysis.
• Skills in Circuit Design and understanding of low‑power techniques and optimization methodologies.
• Demonstrated ability to work collaboratively with cross‑functional engineering teams.
• Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience with tools such as Synopsys, Cadence, or Mentor Graphics is highly desirable.

Having some layout experience is a nice to have not a must have.