ASIC DFT Engineer

Job Description:

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our Fort Collins, Colorado, Development Center. The successful candidate will be responsible for leading DFT programs from chip level DFT specification through implementation and verification, culminating in successfully releasing products to production.

The candidate will work through all phases of SoC DFT activities for APD's designs, including DFT Architecture, test insertion and verification, pattern generation, coverage improvement, post‑silicon debug, and yield improvement to meet product test metrics. The role involves collaboration with the Physical Design & STA team for DFT mode timing closure and may include direct interaction with external customers. Coding skills using TCL, PERL, RUBY, PYTHON, C++ or similar are expected.

• Understand Broadcom & customer DFT feature requirements and DPPM goals, and define appropriate DFT specifications for the ASIC.
• Implement DFT, including Scan, MBIST, TAP, LBIST, IO, Ser Des and other I/P DFT integration.
• Work closely with STA and DI Engineers for design closure of test.
• Generate, verify, and debug test vectors before tape release.
• Validate and debug test vectors on ATE during the silicon bring‑up phase.
• Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
• Interface with customers, physical design, and test engineering/manufacturing teams located globally.
• Collaborate with I/P DFT engineers and other stakeholders.
• Debug customer returned parts on the ATE.
• Innovate newer DFT solutions to solve testability problems in 3nm & beyond.
• Automate DFT & Test Vector Generation flows.

• Strong DFT background (IO, Analog DFT, ATPG, Scan, BIST, etc.).
• Experience with scan insertion and compression (DFT Compiler, Mentor Test Kompress, etc.).
• Logic BIST design and debug experience.
• Proficiency in ATPG vector generation, simulation, and debugging (Tetra Max, Fastscan).
• Verilog coding, testbench generation and simulation skills.
• Memory BIST insertion and verification experience on embedded SRAM, CAM, eDRAM, ROM.
• Boundary‑scan verification and test vector generation; knowledge of IEEE
  1149.1 and IEEE
  1149.6.
• Basic knowledge of Test‑STA and constraints.
• Strong background in IEEE
  1687, I‑JTAG, ICL, and PDL.
• Ability to work in a multi‑disciplined, cross‑department environment.
• Solid knowledge in analog and digital circuit design, and device physics fundamentals.
• Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles.
• Excellent problem‑solving, debug, root‑cause analysis, and communication skills.
• Strong understanding of statistical process control and data analysis techniques for silicon yield improvements and quality metrics.
• Project management capabilities to track and prioritize competing deliverables across cross‑functional stakeholders including Test Engineering, Reliability, and Operations.
• Experience working on ATE is a plus.
• Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug is a plus.
• Experience working on Tessent SSN is a plus.

• Bachelor's degree in Electrical/Electronic/Computer Engineering and 12+ years of relevant industry experience, or Master's degree in Electrical/Electronic/Computer Engineering and 10+ years of relevant industry experience.

The annual base salary range for this position is $127,100 – $203,400.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a comprehensive benefits package:
Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company‑paid holidays, paid sick leave, and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.