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Senior Formal Verification Engineer
Job in
Evansville, Vanderburgh County, Indiana, 47725, USA
Listed on 2026-03-05
Listing for:
Virtual Vocations Inc
Full Time
position Listed on 2026-03-05
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
Key Responsibilities Verify AI-related ASIC designs and features using formal verification methods Collaborate with architecture and RTL teams to specify properties and resolve design issues Develop and implement advanced formal verification methodologies and environments for complex ASIC designs
Required Qualifications BS/MS/PhD or equivalent experience in Computer Science, Computer Engineering, or Electrical Engineering 12+ years of experience in ASIC verification, with 8+ years focused on formal verification methods Mastery of System Verilog Assertions (SVA) and formal property verification Proficient in at least one popular formal verification tool (e.g., Jasper Gold, VC Formal) Good scripting skills for flow automation (e.g., Tcl, Python)
Position Requirements
10+ Years
work experience
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