Senior​/Lead PCIe Engineer

Job Description

Our client is expanding their High Speed IO Team and is looking for experienced Senior and Lead PCIe Engineers with strong background in PCIe architecture and RTL implementation within SoC or ASIC environments.

In this role, you will contribute to the definition, design and integration of PCIe subsystems for advanced semiconductor solutions. A key focus will be ensuring efficient interaction between the PCIe subsystem and processor cores using AMBA CHI based coherency. You will collaborate closely with architecture, RTL, verification and physical design teams to deliver high performance and scalable solutions.

Location
:
Barcelona, Spain - Hybrid

As a Senior / Lead PCIe Engineer
, your broad responsibilities will include but are not limited to:

• Define and implement PCIe architecture and RTL solutions
• Integrate PCIe IP within SoC or ASIC environments
• Ensure optimal interaction between PCIe subsystem and AMBA CHI based cores
• Work with AXI, CHI or AHB protocols where required
• Develop RTL in Verilog or VHDL
• Support block level testing and validation
• Collaborate with cross functional engineering teams
• Contribute to design reviews and technical discussions

Additional Responsibilities for Lead PCIe Engineers Only:

• Drive architectural decisions and technical direction for PCIe subsystems
• Own delivery and quality of PCIe blocks across project milestones
• Coordinate activities across RTL, verification and integration teams
• Mentor and guide engineers within the High Speed IO team
• Support long term roadmap planning for PCIe and related interfaces

• 4+ years of industrial experience for Senior level
• 6+ years of industrial experience for Lead level
• Proven experience in PCIe design or integration
• Experience in SoC or ASIC environments
• Experience with at least one of the following protocols, AXI, CHI or AHB
• Proficiency in RTL design using Verilog or VHDL
• Experience with basic block level testing
• Strong analytical and problem solving skills
• English level C1 or higher

Additional Requirements for Lead PCIe Engineers Only:

• Demonstrated experience owning complex PCIe architectural blocks
• Proven ability to lead technical efforts and coordinate cross functional work
• Strong communication and leadership skills

Our client offers an exciting, challenging role in a collaborative, dynamic environment. The right person will find many career growth opportunities in their company, whether you want to advance your technical skills or aspire to leadership in the future.

• Flexible working hours ( You can work between 7 AM and 7 PM )
• Hybrid model, one day remote per week
• One week per year work from anywhere
• 25 days annual leave plus additional December 24 and 31
• Private medical insurance
• Relocation package including flight, visa support + first month accommodation
• Relocation support for family
• Virtual shares
• Spanish language classes