SW QA Engineer – Radiant Power Calculator Testing

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry.

Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

We are seeking a QA Engineer to validate the Power Calculator feature in the Lattice Radiant software toolchain. This role requires strong technical skills in FPGA design flows, power estimation, and a customer-focused mindset to ensure accurate, reliable, and intuitive power analysis for real-world FPGA designs.

Key Responsibilities:

• Design and execute test plans for Power Calculator workflows, simulating typical customer design scenarios.
• Validate power estimation accuracy across multiple FPGA device families, voltage conditions, and operating modes.
• Perform functional, regression, and performance testing to ensure consistency and usability.
• Simulate customer workflows: import designs, apply constraints, and verify results against expected power profiles.
• Automate test cases using scripting languages (Python, Tcl, Shell) for repeatability and efficiency.
• Analyze discrepancies between calculated and measured power values; collaborate with development teams to resolve issues.
• Integrate real-world IP blocks and reference designs into validation to ensure practical relevance.
• Maintain regression suites and dashboards to monitor feature stability and power analysis trends.
• Provide clear, data-driven reports on validation outcomes, accuracy metrics, and usability feedback.

Required Technical

Skills:

• Strong understanding of FPGA architecture, power estimation concepts, and design constraints.
• Hands-on experience with FPGA design tools, including:
• Lattice Radiant (primary focus)
• Intel Quartus Prime
• AMD Vivado Design Suite
• Familiarity with power analysis methodologies (static and dynamic power estimation).
• Proficiency in scripting for automation (Python, Tcl, Shell).
• Ability to interpret timing and power reports and correlate with design parameters.
• Knowledge of customer workflows: synthesis, place-and-route, timing closure, and power optimization.

Preferred

Skills:

• Experience with Lattice FPGA architectures and Radiant Power Calculator.
• Understanding of thermal and power integrity considerations in FPGA designs.
• Familiarity with version control systems (Perforce) and issue tracking tools (Jira).
• Exposure to CI/CD pipelines and automated test frameworks.

Soft Skills:

• Customer-centric mindset: ability to think like an end-user and anticipate usability issues.
• Strong analytical and problem-solving abilities.
• Excellent communication and collaboration skills.
• Detail-oriented and proactive in identifying quality gaps.