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Memristor implementation of compressive-imaging algorithm revolutionary brain imaging

Job in 2600, Delft, South Holland, Netherlands
Listing for: Neurocomputing Lab
Full Time position
Listed on 2026-02-27
Job specializations:
  • Engineering
    AI Engineer, Robotics
  • IT/Tech
    AI Engineer, Machine Learning/ ML Engineer, Robotics
Salary/Wage Range or Industry Benchmark: 40000 - 60000 EUR Yearly EUR 40000.00 60000.00 YEAR
Job Description & How to Apply Below
Position: Memristor implementation of compressive-imaging algorithm for revolutionary brain imaging [Them[...]

Background: 3D-dimensional ultrasound is a very powerful imaging technique for the brain, but it requires transducers that accommodate thousands of sensors and complex hardware which restricts its use to specialized clinical applications in developed countries. Manufacturing this type of transducers is complex and very costly. We have already proposed a novel approach that uses a technique called compressive sensing and can generate 3D imaging.

The key idea behind this technique is that a simple plastic coding mask placed in front of the ultrasound transducer can compress 3D information requiring far less sensors. This concept extends the imaging capabilities of commercial ultrasound probes from 2D to 3D, but also opens up the possibility for a new type of wearable imaging device for long-time monitoring/imaging of the brain.

Key to deploying this technology is the “inverse calculation” of the ultrasound deformations the plastic mask creates while imaging a target (here: neural tissue in living brains). This calculation involves, as a first step, solving a massive linear system of equations, in the range of 30 GB of data per new imaging target. Current work in the lab involves porting this algorithm onto state-of-the-art GPUs, however we are severely limited by memory-capacity and low-latency concerns, since the system is a streaming, real-time setup.

Thesis goal: The compressive-sensing algorithms have already been ported to an FPGA for accelerated processing. The next step involves further optimizing the existing kernel, exploring alternative implementations and, finally, porting it to a memristor-based platform.

Keywords: HPC, FPGA acceleration, image processing, memristor

Prerequisites: Signal processing (basic), hardware design

Optionally: FPGA design, deep learning (basic)

Contact: Christos Strydis (c.strydis
), Said Hamdioui (S.Hamdioui), Ali Siddiqi (M.A.Siddiqi
)

Miscellaneous: This topic is offered jointly by the Erasmus Medical Center (Neuroscience department) and the Delft University of Technology (Quantum & Computer Engineering department). It capitalizes on the Convergence between the two universities and offers dual working locations (Rotterdam, Delft), access to extended resources and a truly interdisciplinary environment for conducting research.

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