ASIC Emulation Engineer

Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions.

We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.

Cornelis Networks is hiring talented ASIC Design Engineers with deep experience in one or more of the key areas required to build world‑class SoCs deployed in high performance computing, high performance data analytics, and artificial intelligence interconnect solutions.

• Develop and deploy emulation and FPGA models and runtime flows, including maintenance of tests on industry‑standard emulation platforms
• Support enablement and validation of advanced PCIe and Ethernet interfaces; strong familiarity with speed bridges, host software, and peripheral I/O devices (I2C, SPI, UART, SM, JTAG, GPIO)
• Work closely with ASIC, firmware, and software teams to facilitate comprehensive test suite execution and triage across hardware/software boundaries
• Develop, enable, and debug FPGA‑based prototyping and bring‑up flows and driving execution of representative HW/SW workloads
• Debug and develop emulation/prototyping transactors (e.g., PCIe, Ethernet, common and custom peripheral I/O), including root‑causing protocol/throughput issues across the DUT, BFMs, bridges, and host software; enhancing transactor functionality/performance; and creating targeted tests/instrumentation to ensure robust HW/SW co‑verification on platforms
• Leverage AI‑assisted development and analysis tools to accelerate engineering workflows, including (as appropriate): build/runtime flows, log/trace triage, automated issue summarization, script generation, test creation/refinement, documentation, and knowledge capture—while maintaining rigorous validation, reproducibility, and IP/security hygiene
• Provide hands‑on support to Design and DV teams, sharing knowledge of emulation runtime environments and debug methodologies to help resolve issues quickly
• Demonstrate the ability to debug both hardware and software designs down to the individual line of code when necessary

• 10+ years in ASIC design, verification, and emulation/prototyping including successful tape‑outs of complex, high‑performance So Cs
• 5+ years of hands‑on experience with industry leading emulation and FPGA prototyping platforms such as Cadence Palladium/Protium or Synopsys ZeBu/EP1/HAPS
• Hands‑on experience with PCIe (Gen5+) and Ethernet interfaces and protocols, transactor development and debug
• Exposure to HW/SW hybrid bring up environments, including tools such as Helium or VDK
• Strong automation skills including proficiency in scripting languages (TCL, Python, Perl, Shell) to support and enhance automation tools and frameworks
• Familiarity with version control systems (git), project management tools (Jira), and strong communication skills
• Bachelor’s or master’s degree in computer engineering, Computer Science, or Electrical Engineering

• Demonstrated, responsible use of AI‑assisted engineering tools (e.g., for code/scripting acceleration, debug assistance, test generation, or documentation) with an understanding of verification rigor, data sensitivity, and IP protection
• Prototyping experience is a plus (e.g., rapid proof‑of‑concept development, FPGA‑based prototyping, or early bring‑up prototypes to validate architecture, interfaces, or…