RTL Engineer

Overview

RTL Engineer at Glow Networks – Dallas, TX, United States. The RTL Engineer performs detailed block design from system requirements and evolving specifications, RTL coding, lint checks, CDC tests, and timing constraint files, working closely with Synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power, and area goals.

• Develop hardware architecture from specification documents.
• Write RTL code for IP development and RTL integration, checking code for lint/CDC issues, synthesizability and timing quality, and low‑power implementation.
• Support verification team with debugging and support physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL.
• Develop and execute low‑power design (UPF/CPF).
• Design top‑level RTL, integration of blocks, clocks, resets, configuration registers.
• Knowledge of JESD
  204C block design and related design/verification experience (including licensed IP & PHY from third parties).
• Awareness of DFT concepts to fix functional violations that may be introduced, incorporating DFT structures.
• Carry out static checks including lint/CDC (Spyglass), synthesis, LEC, and STA; debug and fix functional breaks.
• Take ownership of tasks and drive them to closure.

• Bachelor's or master’s in electrical or computer engineering or related field.
• 12+ years of experience in logic (RTL) design.

• Experience with advanced peripheral bus IPs such as GPIO, UART, SPI, SW, JTAG, and I2C.
• Strong fundamentals in VLSI design and digital design architecture.
• Strong problem‑solving and data analysis skills.
• Proficiency in scripting languages such as Perl, TCL, Python.
• Excellent interpersonal skills and ability to work with remote teams.
• Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data‑driven approach.
• Knowledge of low‑speed bus protocols (AMBA/OCP) and high‑speed serial protocols (PCIe/USB/Ethernet) used at various stages of the design.