FE Engineer

Cupertino, California, United States Hardware

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APPLE INC has the following available in Cupertino, and various unanticipated locations throughout the USA. RTL design (System Verilog coding) for the digital logic in Power Management ICs (PMICs). These ICs are mixed signal ICs and contain a lot of digital control logic. RTL design is the primary responsibility of a “front-end” engineer in the VLSI design process. RTL simulation and functional verification of designs using Cadence’s Xcelium and Simvision.

All the designs are simulated, and the waveforms are assessed to verify functionality. Synthesize RTL designs into ASIC gates and analyze Power, Performance and Area impact using Synopsys’s Design Compiler or Cadence Genus synthesis tool. Firmware development using the C language for various processes in the PMICs including temperature management, SoC voltage and current monitoring. Script in Perl and Python for ASIC flow development tasks.

Run Clock Domain Crossing simulations for the digital logic in PMICs. Run Reset Domain Crossing simulations for the digital logic in PMICs. General design signoff duties; SDC, CDC and other constraints files cleanup. Deliver FPGA build of the PMICs to facilitate platform emulation with the SoC.. Interact with the Silicon Validation team to help them understand design, review test plan, and provide debugging support.

Interact with different teams such as Analog Design, Architecture, DFT and ATE to finalize design specifications and fulfill all product requirements. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $156,853 - $220,900/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS:
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including:
Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits:  Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

• Master's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field and 2 years of experience in the job offered or related occupation.
• Experience and/or education must include:
• Simulating designs using Cadence or Verilog Simulators.
• Analyzing circuit behavior in Cadence Indago or waveform viewers.
• Synthesizing design into ASIC library gates using Synopsys Design Compiler or Cadence Genus.
• Understanding CDC techniques and ensuring their correct implementation in SV.
• Performing chip tapeout signoff duties, including the review of constraint files and STA reports.
• Running SPICE simulations of circuits for buffer and interconnect delay analysis.
• VLSI flow automation using PERL and TCL scripts.

• N/A

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .

Apple accepts applications to this posting on an ongoing basis.