Sr. PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning; AWS

Overview

Our Machine Learning Acceleration (MLA) team develops the Inferentia and Trainium SOCs that are used to power today’s AI workloads in datacenters all around the world. As a Circuit & Design Analysis engineer, you’ll collaborate with multiple teams to drive improvements in silicon yield & performance - it’s still Day One here at Amazon!

• Design and implement custom cells / IP.
• Develop & run characterization flows for custom cells / IP developed.
• Own integration & post-silicon qualification of IPs like PLL, PCIE, UCIE, HBM, sensors/monitors.
• Develop scripts to automate running analysis and collect reports.
• Develop test-plan and perform measurements in the lab to correlate with simulation data.
• Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers, product engineers, hardware engineers as well as with the RTL/Arch. teams.

• Evaluate IPs (like sensors, process monitors) from a 3rd party
• Develop & characterize custom IPs like ganged buffers, custom logic cells for specialized operations (like MACs)
• Work with designers and architects to identify pain-points and areas where custom solutions can improve PPAS
• Do post-silicon quality checks for key IP like PLLs, UCIE/PCIE, HBM
• Do post-silicon power measurements of jitter, sensor calibration, power and correlate with simulation

• 8+ years of ASIC implementation, synthesis, STA and physical design in deep sub‑micron nodes (16nm or smaller) experience
• BS degree in computer science, computer engineering, or related field
• Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area
• Experience in Python, Perl, or another scripting language
• Understanding of other sign‑off activities (ir/em, physical verification, timing closure, DFT)
• Expertise on circuit level analysis using tools like SPICE / SPECTRE
• Expertise in interconnect & transistor fundamentals in deep sub‑micron processes

• Master's degree or Ph.D. degree in Electrical Engineering or related field
• Experience in RTL coding and debug, as well as performance, power, area analysis and trade‑offs
• Experience with modern ASIC/FPGA design and verification tools
• Experience with SOC bring‑up and post-silicon validation

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

USA, CA, Cupertino

Base salary range: $ - $ USD annually