EMIR Engineer II, Annapurna Labs - Cloud Scale Machine Learning; AWS

Our Machine Learning Acceleration (MLA) team develops the Inferentia and Trainium SoCs that are used to power today’s AI workloads in datacenters all around the world. As a Sr. SoC EMIR Engineer, you’ll contribute to the EMIR sign‑off of our SoCs and help maintain a high bar on quality.

We’re searching for an experienced EMIR engineer with a proven track record of handling challenges  this role, you’ll be working directly with architects, designers, verification engineers, power integrity engineers and physical design experts – defining best practices in power grid design, developing test cases & vectors to model demand currents accurately, modeling & signing‑off EMIR taking into account board and package impact, advancing the state‑of‑the‑art in EMIR analysis and modeling.

• Design & analyze power grids
• Setup flows for EMIR analysis
• Run EMIR analysis for large subsystems, So Cs
• Partner with EDA tool vendors to develop / evaluate new methodologies for EMIR analysis
• Develop and maintain dashboards for EMIR rollups
• Work with designers, architects, Verification engineers and Physical Design engineers to develop vectors for IR analysis, Thermal analysis and power estimation

• Design and evaluate power grids
• Work with designers, architects and verification engineers to come up with worst‑case vectors for power and IR analysis
• Root cause causes of low annotation or low switching coverage with vectors
• Develop & maintain dashboards to track EMIR status
• Root cause causes of IR drop and suggest solutions to fix
• Combine IR analysis of SoC with IR at board and package level (concurrent IR analysis)
• Do post‑silicon power measurements and correlate with simulation
• Innovate on ways to model VR, board and package impact on voltage drop more accurately
• Partner with EDA tool vendors to develop / evaluate new methodologies for EMIR analysis

We are a start‑up like team where no‑one says “this is not my job” and you won’t find anyone telling you to stay in your lane. This is a fast‑paced, intellectually challenging position, and you’ll work with thought‑leaders in multiple technology areas. We encourage collaboration and teamwork with multiple teams and engineers including architects, RTL designers, Verification engineers, Physical Design engineers, Emulation engineers and software engineers.

• Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills
• Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing
• Bachelor’s degree in Electrical Engineering or a related field, or experience in RTL coding and debug, as well as performance, power, area analysis and trade‑offs
• Experience with a scripting language such as Power Shell, Python, Bash, Perl, Ruby or similar
• Expert on EMIR analysis tools like Redhawk‑SC or Voltus or similar
• Deep, circuit‑level understanding of power, EM and IR
• Good understanding of Physical Design, EM/IR, Power Integrity, and Thermal at the die, package, board, and server level

• Master’s degree in Electrical or Communications Engineering or a related field
• Experience with formal verification techniques including abstraction and end‑to‑end checking
• Experience with ARM and various DSP ISAs
• Familiarity with Make or similar for automation of EMIR rollups
• Experience with RTL design (System Verilog)
• Experience with PnR tools (Fusion Compiler or Innovus)
• Familiarity with Power analysis tools (Prime Power or similar)
• Familiarity with timing analysis tools (Prime Time or similar)
• Some experience with lab equipment and capable of doing lab power analysis

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