Rtl Design Engineer

RTL Design Engineer

Building AI chips that are hard‑coded for individual model architectures.

As an RTL Engineer, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both our existing and upcoming ASIC designs.

In this role, you will work closely with state‑of‑the‑art architectures for machine learning. You do not need to have experience working with these yet, but you will be willing and able to learn quickly. You will work in a fast‑paced environment with a high degree of autonomy, and be responsible for a key part of the team’s success.

• Implement a block to efficiently compute floating point math operators
• Provide feedback to the uArch team to make sure blocks meet timing and area constraints

• At least 5 years of work experience in RTL development.
• Experience with high‑speed digital logic.
• Proficiency in standard RTL design and synthesis tools
• Familiarity with verification work and writing test benches
• Are able to learn quickly about transformers and other aspects of modern artificial intelligence
• Willing to start quickly

• Experience with PCIe, Ethernet, or HBM technologies
• Familiarity with transformer models and machine learning.
• Familiarity with numerical representations and functions
• Ability to program with Python or another scripting language

Location:

Cupertino, CA, United States