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Engineering Design & Technologists

ASIC Timing Engineer - Signoff, STA & Flow

Job in Cupertino, Santa Clara County, California, 95014, USA
Listing for: Apple Inc.
Full Time position
Listed on 2026-01-11
Job specializations:
  • Engineering
    Engineering Design & Technologists
Job Description & How to Apply Below
A leading technology company in California seeks an ASIC STA Engineer to manage timing sign-off and develop timing constraints. Candidates should have a BS degree and at least 3 years of relevant experience, with a strong knowledge of ASIC timing closure flow, and expertise in STA tools. The position offers a competitive salary, stock opportunities, and comprehensive employee benefits including medical, dental, and educational reimbursement.
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