Senior ASIC Verification Engineer; SystemVerilog/UVM
Job in
Broomfield, Boulder County, Colorado, 80020, USA
Listed on 2026-02-28
Listing for:
Broadcom
Full Time
position Listed on 2026-02-28
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Test Engineer, Engineering Design & Technologists
Job Description & How to Apply Below
Location: Broomfield
A leading technology company in the United States is seeking a Constrained Random Design Verification Engineer. The candidate will work on developing silicon products for Ethernet systems, focusing on verification methodologies like System Verilog and UVM. Responsibilities include collaborating with design teams and ensuring coverage closure. This position offers a competitive salary range of $108,000 - $172,800, along with a comprehensive benefits package.
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Position Requirements
10+ Years
work experience
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