FPGA Engineer

A leading proprietary trading firm is expanding its FPGA engineering teams in New York City and Chicago. The group builds ultra‑low‑latency hardware systems that power the firm’s global trading infrastructure.

• Architect and implement new FPGA applications from the ground up, including RTL design, synthesis, place & route, static timing analysis, and documentation.
• Develop custom logic and complex RTL architectures optimized for latency, throughput, and reliability.
• Research, evaluate, and prototype cutting‑edge FPGA hardware platforms and emerging technologies.
• Propose innovative solutions to overcome device‑level and architectural constraints.
• Work closely with software engineers, systems engineers, and other hardware teams to integrate FPGA solutions into production‑grade trading systems.
• Perform lab‑level debugging, characterization, and validation of new hardware designs.
• Own FPGA projects end‑to‑end-from requirements and feasibility evaluation through design, verification, deployment, and ongoing optimization.

• Bachelor's degree or higher in Computer Engineering, Electrical Engineering, or related fields (Master's/PhD counts toward experience).
• 3+ years of hands‑on experience in FPGA or hardware design engineering.
• Strong RTL design experience with 2+ years of production‑level Verilog development.
• Demonstrated experience creating custom logic and building complex RTL systems.
• Proven ability to take FPGA projects from concept → architecture → implementation → deployment.
• Deep understanding of FPGA design flows, including synthesis, place & route, and static timing analysis.
• Experience designing system‑on‑chip (SoC) architectures, memory/processor subsystems, networking interfaces, and peripheral interconnects.
• Working knowledge of the TCP/IP networking stack.
• Strong experience with Xilinx or Intel/Altera FPGA tool chains and device families.
• Familiarity with functional verification methodologies (System Verilog, UVM, testbench development) is a strong plus.
• Ability to quickly assess feasibility of FPGA‑based solutions given device constraints and latency/throughput requirements.
• Experience designing ultra‑low‑latency hardware pipelines and optimizing critical timing paths.
• Understanding of high‑speed serial protocols (e.g., PCIe, Ethernet, JESD, Aurora).
• Experience with hardware‑software co‑design and integration.
• Exposure to network protocol offload engines, FPGA‑based NICs, or packet processing logic.
• Comfort working in fast‑paced, high‑ownership environments with tight feedback loops.