Principal Engineer - CAD; Physical Verification

Principal Engineer - CAD (Physical Verification)

Join to apply for the Principal Engineer - CAD (Physical Verification) role at Microchip Technology Inc.

The CAD group at Microchip offers global support for multiple technology nodes and tools used in product development, providing innovative solutions for the design community. The candidate will focus on flow development and support for back end physical verification. If you have a solid software background and are interested in supporting semiconductor chip design, this may be the job for you.

Expertise using Siemens Calibre and/or Cadence Pegasus DRC, LVS and PERC tools is paramount. The ideal candidate should be able to run the tools, debug results, develop verification run decks, and automate flow procedures. A strong understanding of both the digital and analog sides of design, including circuit/electrical and layout/physical knowledge, is essential.

• Develop physical verification regression test cases to QA physical verification decks.
• Support Layout and Design engineers with physical verification activities using tools such as Siemens Calibre, Cadence Pegasus, or Synopsys Hercules.
• Utilize advanced EDA methods to support ESD, ERC, Voltage‑Aware DRC, via‑doubling methodologies, etc.
• Work with Technology Development and Device Engineering to develop DRC rules, additional devices, and design‑for‑manufacturability checks.
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Develop rule decks as needed to support flow and verify/enhance foundry rule decks.
• Support remote sites worldwide with layout verification activities and debug of physical verification issues.
• Collaborate with the team to develop flows that improve the quality and reliability of devices.
• Build regression test cases for various PDKs from 4 nm to 600 nm across multiple foundries.

• Bachelor’s degree with 10+ years developing and supporting physical verification activities, or Master’s degree with 7.5+ years.
• In‑depth knowledge of Calibre Design Rev scripting, SVRF and TVF.
• Proficiency in debugging PV issues with RVE, Vue, or other EDA visualizers.
• Experience customizing Calibre Interactive, proficient with Tcl/Tk, Perl, Python and other scripting languages.
• Solid knowledge of layout rules, device identification, and foundry rules.
• Strong knowledge of Design for Manufacturing solutions affecting quality, reliability, and yield.
• Extensive knowledge of Calibre/Pegasus/Hercules syntax and semantics, or similar layout verification tool.
• Strong knowledge of Cadence Virtuoso and/or Calibre
  
  DRV; preferably Extraction, Reliability and Dynamic Noise related knowledge.
• Excellent verbal and written communication and interpersonal skills.

0%‑25%

80% sitting, 10% standing, 10% walking, 100% inside.

The annual base salary range for this position in the US is $75,000 – $232,000*, dependent on location, skills and experience.

Application window will remain open until qualified candidates have been identified.

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected veteran status, age, or any other characteristic protected by law.

For more information on applicable equal employment regulations, please refer to the “Know Your Rights:
Workplace Discrimination is Illegal” poster.

Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.